1. Field of the Invention
The present invention relates to a solid-state image sensing device such as a CMOS image sensor, and is applied to, e.g., a cell phone with an image sensor, a digital camera, and a video camera.
2. Description of the Related Art
A CMOS image sensor is used in, e.g., a cell phone with an image sensor, a digital camera, and a video camera. A CMOS image sensor of this type performs a noise reducing operation (called CDS: Correlated Double Sampling) during analog-to-digital conversion of a readout signal charge. Also, the CMOS image sensor includes two stages of A/D converters in order to perform high-accuracy A/D conversion. Furthermore, a shift register circuit or decoder circuit is generally used as a vertical line selection circuit (e.g., Japanese Patent No. 3361005).
The CMOS image sensor as described above performs a thinning operation which reads two pixel lines and skips two pixel lines arranged in the vertical direction during a monitoring operation for reducing the number of pixels. When this thinning operation is performed, however, sampling points of G signals (a Gr signal and Gb signal) for generating a luminance signal become discontinuous in a color sensor having a Bayer pattern, so a spurious signal deteriorates the image quality.
As a measure to cope with this deterioration in image quality cause by a spurious signal, Jpn. Pat. Appln. KOKAI Publication No. H09-247535 has proposed a technique which averages vertical signals by using capacitors. However, the addition of the capacitors increases the pattern occupation area, or buffer circuits formed in one-to-one correspondence with the capacitors increase the power consumption.
Accordingly, demands have arisen for a solid-state image sensing device capable of preventing the deterioration in image quality caused by a spurious signal without increasing the pattern occupation area or power consumption.